A bipolar transistor consisting of an emitter, collector, and intervening base is typically created in a vertical arrangement along a major surface of a semiconductor body. Referring to the drawings, FIG. 1 illustrates a conventional vertical NPN transistor of the type described in Stolfa et al, "A BiCMOS 0.8 .mu.m PROCESS WITH A TOOLKIT FOR MIXED-MODE DESIGN," IEEE Cust. Integ. Circs. Conf., 9-12 May 1993, pp. 24.2.1-24.2.4. The transistor in FIG. 1 is created from a silicon semiconductor body consisting of P- substrate 10 and overlying N epitaxial layer 12. N+ buried layer 14 lies along the metallurgical interface between substrate 10 and epitaxial layer 12. Field-oxide region 16 is partially sunk into the semiconductor body along the upper surface of layer 12.
P base region 18 and N+ emitter region 20 are situated in epitaxial layer 12 with base region 18 abutting field oxide 16. The collector is formed with N+ buried layer 14 and the portion of N epitaxial layer 12 lying below base region 18. Small portions of epitaxial layer 12 situated to the sides of base region 18 also invariably act as part of the collector. Items 22 and 24 in FIG. 1 respectively indicate the collector-base and emitter-base junctions. The transistor further includes P+ base contact zone 26 and N+ collector contact zone 28.
Base region 18 and emitter region 20 are formed by introducing suitable P-type and N-type dopants into epitaxial layer 12 through appropriate parts of its upper surface to respectively define junctions 22 and 24. The P-type doping typically entails (a) ion implanting a boron-containing species into layer 12 using a suitable shield to control where the dopant enters layer 12 and (b) annealing the semiconductor body to active the implanted boron and drive it further into layer 12.
The shield used during the P-type ion implantation, commonly referred to as the "base implant", consists of part of field oxide 16. The base-implant shield often includes photoresist, the location of which is indicated by dotted line 30 in FIG. 1. As schematically illustrated by arrows 32 in FIG. 1, the base implant is performed in a direction perpendicular, or nearly perpendicular, to the upper epitaxial surface. In a typical case, the base implantation is done at a tilt angle of 7.degree. relative to the vertical--i.e., the direction generally perpendicular to the upper epitaxial surface--to reduce undesired channeling along the crystal structure.
During the subsequent anneal, part of the implanted P-type dopant diffuses downward and sideways to establish collector-base junction 22 in FIG. 1. The lateral diffusion rate is slightly less than the vertical diffusion rate.
The prior art transistor of FIG. 1 operates in the following manner. When the base-to-emitter voltage is raised to a suitable value, electrons in emitter region 20 move downward across base region 18 and the underlying part of epitaxial layer 12 to buried layer 14. The electrons then move laterally along buried layer 14 and vertically up collector contact zone 28 to the upper epitaxial surface. Even though the current flow through base region 18 is largely in the vertical direction, some electrons pass laterally through the edges of base region 18. The lateral current flow can significantly affect transistor operation and thus needs to be considered in assessing transistor performance.
An important transistor characteristic is the collector-to-emitter breakdown voltage BV.sub.CEO with the base open (unconnected). BV.sub.CEO is the approximate value of the collector-to-emitter voltage V.sub.CE at which the collector current starts to increase very rapidly with small V.sub.CE increases. This can occur by avalanche charge-carrier multiplication or punch-through. At punch-through, the depletion region of the collector-base junction extends to the depletion region of the emitter-base junction. The diffusion-limited quasi-neutral zone normally situated between the two regions is eliminated, thereby allowing the number of charge carriers that pass through the base to increase rapidly in an undesirable manner with increasing V.sub.CE.
The thickness of base region 18 in the lateral direction for the prior art device of FIG. 1 differs from the base thickness in the vertical direction. In particular, the minimum base thickness t.sub.BL in the lateral direction can be greater than or less than the minimum base thickness t.sub.BV in the vertical direction. As indicated in FIG. 1, minimum lateral base thickness t.sub.BL occurs at the upper semiconductor surface. Minimum vertical base thickness t.sub.BV is also approximately the average vertical base thickness. The specific relationship between thicknesses t.sub.BL and t.sub.BV depends on the mechanics of the base implant and diffusion and on the amount D.sub.OS by which the edge of photoresist 30 is offset from the edge of emitter region 20 at the t.sub.BL location along the upper semiconductor surface.
If t.sub.BL is less than t.sub.BV in the transistor of FIG. 1, base region 18 first becomes punched through along its lateral edge at the t.sub.BL location. When collector-to-emitter breakdown voltage BV.sub.CEO is controlled by punch-through, BV.sub.CEO is reduced. Collector-to-emitter leakage current I.sub.CEO is increased. Both of these effects are undesirable. In short, the transistor characteristics are significantly degraded when t.sub.BL is less than t.sub.BV.
By setting offset distance D.sub.OS at a sufficiently high value, t.sub.BL is greater than t.sub.BV. However, this typically requires that the lateral area occupied by the transistor be increased, an undesirable result. Specifically, base region 18 bulges out laterally a distance D.sub.BLG beyond the vertical t.sub.BL shadow due to the mechanics of the base implant and diffusion. Bulge distance D.sub.BLG is typically large compared to t.sub.BL. In the illustrated example, D.sub.BLG is greater than t.sub.BL.
If offset D.sub.OS is increased by a certain amount so as to make t.sub.BL greater than t.sub.BV, bulge distance D.sub.BLG is shifted to the left in FIG. 1 by the same amount, thereby increasing the lateral dimension of base region 18. This necessitates a corresponding increase in the lateral dimension of the transistor if the spacing between base region 18 and collector contact 28 is to be held constant in order to avoid further lateral transistor action. It would be desirable to have a technique for increasing thickness t.sub.BL without increasing thickness t.sub.BV, and preferably capable of setting t.sub.BL at a value equal to or greater than t.sub.BV without significantly increasing the transistor area.
The problem of excessively small lateral base thickness is also of concern in an oxide-isolated vertical bipolar transistor where the emitter is walled--i.e., part of the emitter contacts the isolation oxide Ratnam et al, "The effect of Isolation Edge Profile on the Leakage and Breakdown Characteristics of Advanced Bipolar Transistors," IEEE Bipolar Circs. & Tech. Meeting, 7-8 Oct. 1992, pp. 117-120, addresses this matter.
FIG. 2 illustrates a profile of a walled-emitter vertical NPN transistor computer simulated in Ratnam et al. The simulated transistor contains N- collector region 34, P base region 36, and N+ emitter region 38, all consisting of monocrystalline silicon. Regions 34-38 all abut an internal sidewall of field-oxide region 40. N+ emitter region 38 is created in a self-aligned manner by dopant out-diffusion from overlying N+ polysilicon emitter contact 42. Items 44 and 46 are the collector-base and emitter-base junctions.
Field-oxide region 40 in FIG. 2 is in the shape of the well-known "bird's beak" where regions 36 and 38 abut field oxide 40. The bird's beak shape of field oxide 42 causes the minimum thickness t.sub.BW of base region 36 along the sidewall of field oxide 40 to be significantly less than the minimum vertical base thickness t.sub.BV in the vertical direction. As discussed in Ratnam et al, this significantly increases leakage current I.sub.CEO and reduces breakdown voltage BV.sub.CEO. Ratnam et al indicate that the problem of t.sub.BW being less than t.sub.BV can be significantly alleviated by providing the field oxide with a largely vertical sidewall. However, this requires extra processing. Analogous to the transistor of FIG. 1, it would be desirable to have a technique for increasing thickness t.sub.BW without having to employ the extra processing needed to eliminate the bird's beak.